A programmable logic device (PLD), such as a Field Programmable Gate Array (FPGA), is an integrated circuit that may be programmed to perform specified logic functions. The PLD typically includes an array of programmable logic blocks that may be programmed with an intellectual property (IP) core. It is appreciated that the IP core may be proprietary configuration data for a variety of commonly-used functions. The IP core may be vendor-provided and may be sold either by a manufacturer of the PLD or by a third party, freeing a customer of the manufacturer from programming the functions on its own.
The IP core can include a predetermined set of configuration data bits that program the PLD to perform one or more functions. Logic and connectivity of a design in the PLD can be represented by or be mapped by the IP core. The IP core can provide, but are not limited to providing, Digital Signal Processing (DSP) functions, storage function, logic functions, and math functions.
The PLD is typically configured using a dedicated control block in a rigid and sequential manner. A configuration stage completes before the PLD can be used. However, having a rigid configuration sequence limits and constrains use of the PLD in a variety of applications. Consequently, it is desirable to provide improved mechanisms for configuring the PLD.